Design and Implementation of 8K-bits Low Power SRAM in 180nm Technology

This paper explores the tradeoffs that are involved in the design of SRAM. The major components of an SRAM such as the row decoders, the memory cells and the sense amplifiers have been studied in detail. The circuit techniques used to reduce the power dissipation and delay of these components has been explored and the tradeoffs have been explained. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bitlines and the data lines. Clocked voltage sense amplifiers are essential for obtaining low sensing power, and accurate generation of their sense clock is required for high speed operation. The tracking circuits essentially use a replica memory cell and a replica bitline to track the delay of the memory cell over a wide range of process and operating conditions. We present experimental results from two different prototypes. Finally an 8Kb prototype SRAM has been designed and verified. This design incorporates some of the circuit techniques used to reduce power dissipation and delay. Experimental data has been provided which shows the effectiveness of using the resetting scheme for the row decoders. While designing the SRAM, techniques such as circuit partitioning, gate oxide thickness variations and low power layout techniques are made use of to minimize the power dissipation. The mask design of the constituent memory blocks is done using virtuoso tool, the DRC & LVS verified through Hercules/Calibre. The design was simulated at a clock speed of 500 MHz. The read access time was found to be 0.85ns while the write access time was found to be 0.42ns at pre-layout simulations. The total power dissipation was 10.232mW at pre-layout simulations. The read access time was found to be 1.23ns while the write access time was found to be 0.85ns at post-layout simulations.The total power dissipation was 20.521mW at post-layout simulations.